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5. Pin Descriptions of Major Components
5.1 AMD Mobile K8 CPU - 1
DDR SDRAM Memory Interface Pins DDR SDRAM Memory Interface Pins (Continued)
Signal Name Type Description Signal Name Type Description
MEMCLK_H/L[7] O-IOD Differential DDR SDRAM clock to the top of DIMM 0 for MEMADDA[13:0] O-IOS DRAM Column/Row Address. Two copies are provided to
unbuffered DIMMs.1 MEMADDB[13:0] accommodate the loading of unbuffered DIMMs. During
MEMCLK_H/L[6] O-IOD Differential DDR SDRAM clock to the top of DIMM 1 for precharges, activates, reads, and writes, the two copies are
unbuffered DIMMs.1 inverted from each other (except A[10] which is used for
MEMCLK_H/L[5] O-IOD Differential DDR SDRAM clock to the bottom of DIMM 0 for auto-precharge) to minimize switching noise. The signals are
unbuffered DIMMs.1 inverted only when the bus is used to carry address
MEMCLK_H/L[4] O-IOD Differential DDR SDRAM clock to the bottom of DIMM 1 for information.1
unbuffered DIMMs.1 MEMBANKA[1:0] O-IOS DRAM Bank Address. Two copies are provided to
MEMCLK_H/L[3] O-IOD Differential DDR SDRAM clock to DIMM 3 for registered MEMBANKB[1:0] accommodate the loading of unbuffered DIMMs. During
DIMMs.1 precharges, activates, reads, and writes the two copies are
MEMCLK_H/L[2] O-IOD Differential DDRS DRAM clock to DIMM 2 for registered inverted from each other to minimize switching noise. The
DIMMs.1 signals are inverted only when the bus is used to carry address
information.1
MEMCLK_H/L[1] O-IOD Differential DDR SDRAM clock to the middle of DIMM 1 for
unbuffered DIMMs, or DIMM 1 for registered DIMMs.1 MEMRESET_L O-IOS DRAM Reset pin for Suspend-to-RAM power management
MEMCLK_H/L[0] O-IOD Differential DDR SDRAM clock to the middle of DIMM 0 for mode. This pin is required for registered DIMMs only.
unbuffered DIMMs, or DIMM 0 for registered DIMMs.1 MEMVREF VREF DRAM Interface Voltage Reference 1
MEMCKEA O-IOS Clock Enables to DIMMs. Used to gate clocks for power MEMZP A Compensation Resistor tied to VSS 1
MEMCKEB management functionality.1 MEMZN A Compensation Resistor tied to 2.5 V 1
MEMDQS[17:0] B-IOS DRAM Data Strobes synchronous with MEMDATA and
MEMCHECK during DRAM read and writes.1 Notes:
1. For connection details and proper resistor values, see the AMD Athlon? 64 Processor
MEMDATA[63:0] B-IOS DRAM Interface Data Bus
Motherboard Design Guide, order# 24665
MEMCHECK[7:0] B-IOS DRAM Interface ECC Check Bits
MEMCS_L[7:0] O-IOS DRAM Chip Selects 1
MEMRASA_L O-IOS DRAM Row Address Select. MEMRASA_L and
MEMRASB_L MEMRASB_L are functionally identical. Two copies are
provided to accommodate the loading of unbuffered DIMMs.1Clock Pin Descriptions
Signal Name Type Description
MEMCASA_L O-IOS DRAM Column Address Select. MEMCASA_L and
MEMCASB_L MEMCASB_L are functionally identical. Two copies are CLKIN_H/L I-IOD 200-MHz PLL Reference Clock
provided to accommodate the loading of unbuffered DIMMs.1FBCLKOUT_H/L O-IOD Core Clock PLL 200-MHz Feedback Clock
MEMWEA_L O-IOS DRAM Write Enable. MEMWEA_L and MEMWEB_L are
MEMWEB_L functionally identical. Two copies are provided to accommodate
the loading of unbuffered DIMMs.1
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