8175 N/B MAINTENANCE8175 N/B MAINTENANCE
5.3 Intel 82801BA(I/O Controller HUB )
PCI Interface Signals IDE Interface Signals(continued)
Name Type Description Name TypeDescription
PME# I PCI Power Management Event: PCI peripherals drive PME# to PDA[2:0], O Primary and Secondary IDE Device Address: These output signals
wake the system from low-power states S1-S5. PME# assertion can SDA[2:0] are connected to the corresponding signals on the primary or
secondary IDE connectors. They are used to indicate which byte in
also be enabled to generate SCI from the S0 state. In some cases the
ICH2 may drive PME# active due to an internal wake event. The either the ATA command block or control block is being addressed.
ICH2 will not drive PME# high, but it will be pulled up to VccSus3_3 PDD[15:0], I/O Primary and Secondary IDE Device Data: These signals directly
by an internal pull-up resistor. SDD[15:0] drive the corresponding signals on the primary or secondary IDE
CLKRUN# I/O PCI Clock Run: For the ICH2-M, CLKRUN# is used to support PCI connector. There is a weak internal pull-down resistor on PDD[7] and
(ICH2-M only) Clock Run protocol. This signal connects to PCI devices that need to SDD[7].
request clock re-start or prevention of clock stopping. PDDREQ, I Primary and Secondary IDE Device DMA Request: These input
REQ[A]# / I PC/PCI DMA Request [A:B]: This request serializes ISA-like DMA SDDREQ signals are directly driven from the DRQ signals on the primary or
GPIO[0] Requests for the purpose of running ISA-compatible DMA cycles secondary IDE connector. It is asserted by the IDE device to request a
REQ[B]# / over the PCI bus. This is used by devices such as PCI-based Super data transfer, and used in conjunction with the PCI bus master IDE
REQ[5]# / I/O or audio codecs that need to perform legacy 8237 DMA but have function. They are not associated with
GPIO[1] no ISA bus. any AT-compatible DMA channel. There is a weak internal
When not used for PC/PCI requests, these signals can be used as pull-down resistor on these signals.
General Purpose Inputs. Instead, REQ[B]# can be used as the 6th PCI PDDACK#, O Primary and Secondary IDE Device DMA Acknowledge: These
bus request. SDDACK# signals directly drive the DAK# signals on the primary and secondary
GNT[A]# / O PC/PCI DMA Acknowledges [A:B]: This grant serializes an IDE connectors. Each signal is asserted by the ICH2 to indicate to the
GPIO[16] ISA-like DACK# for the purpose of running DMA/ISA master cycles IDE DMA slave devices that a given data transfer cycle (assertion of
GNT[B]# / over the PCI bus. This is used by devices such as PCI-based Super/IO DIOR# or DIOW#) is a DMA data transfer cycle. This signal is used
GNT[5]# / or audio codecs which need to perform legacy 8237 DMA but have in conjunction with the PCI bus master IDE function and are not
GPIO[17] no ISA bus. associated with any AT-compatible DMA channel.
When not used for PC/PCI, these signals can be used as General PDIOR# O Primary and Secondary Disk I/O Read (PIO and Non-Ultra
Purpose Outputs. GNTB# can also be used as the 6th PCI bus master SDIOR# DMA): This is the command to the IDE device that it may drive data
grant output. These signal have internal pull-up resistors. on the PDD or SDD lines. Data is latched by the ICH2 on the
deassertion edge of PDIOR# or SDIOR#. The IDE device is selected
either by the ATA register file chip selects (PDCS1# or SDCS1#,
PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA
IDE Interface Signals acknowledge (PDDAK# or SDDAK#).
Name Type Description Primary and Secondary Disk Write Strobe (Ultra DMA Writes to
Disk): This is the data write strobe for writes to disk. When writing to
PDCS1#, O Primary and Secondary IDE Device Chip Selects for 100 Range:
disk, ICH2 drives valid data on rising and falling edges of PDWSTB
SDCS1# These signals are for the ATA command register block. This output or SDWSTB.
signal is connected to the corresponding signal on the primary or Primary and Secondary Disk DMA Ready (Ultra DMA Reads
secondary IDE connector.
from Disk): This is the DMA ready for reads from disk. When
PDCS3#, O Primary and Secondary IDE Device Chip Select for 300 Range: reading from disk, ICH2 deasserts PRDMARDY# orSRDMARDY#
SDCS3# These signals are for the ATA control register block. This output to pause burst data transfers.
signal is connected to the corresponding signal on the primary or
secondary IDE connector.
125
MiTac Secret
Confidential Document |
ACEC
